Low voltage read cascode for 2V/3V and different bank combinations without metal options for a simultaneous operation flash memory device

ABSTRACT

A pre-amplifier portion of a sense amplifier for a dual bank architecture simultaneous operation flash memory device is provided. The sense pre-amplifier circuit includes two inverting amplifiers, the second inverting amplifier providing a feedback loop for the first inverting amplifier. In addition, special “kicker” circuitry raises the sense pre-amplifier&#39;s input signal line to its operating level. The combination of inverting amplifiers, feedback loop and level raising circuitry is configured to provide higher bandwidths for the sense pre-amplifier to accommodate low capacitive loading resulting from a small memory bank. The combination is also configured to provide faster raising of the input signal line to operating level to accommodate high capacitive loading resulting from a large memory bank. The combination is also configured to provide increased signal margins at the output of the sense pre-amplifier.

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BACKGROUND

Computers, personal digital assistants, cellular telephones and otherelectronic systems and devices typically include processors and memory.The memory is used to store instructions (typically in the form ofcomputer programs) to be executed and/or data to be operated on by theprocessors to achieve the functionality of the device. In someapplications, the systems and devices may require that the instructionsand/or data be retained in some form of a permanent/non-volatile storagemedium so that the information is not lost when the device is turned offor power is removed. Exemplary applications include computer BIOSstorage and diskless handheld computing devices such as personal digitalassistants.

One way to provide such non-volatile storage capability is to include amass-storage device such as a hard disk drive. Hard disk drives aremechanical devices which store data on rotating magnetic platters.However, such devices may be difficult to fit in small systems and mayhave significant reliability, cost and manufacturing constraints. Analternative to such devices are integrated-circuit based non-volatilememories. One type of non-volatile memory that can be used is ErasableProgrammable Read Only Memory (“EPROM”). While conventional EPROM'sprovide reliable non-volatile storage, they may not be able to bereprogrammed in the field in a practical manner. For example, EPROM'stypically require exposure to ultraviolet light to erase them which mayrequire that the EPROM memory chips be removed from the device. Onceerased and reprogrammed, they are placed back in the device. In manyapplications, removing the memory to reprogram the device is notpractical. In addition, besides not being easily reprogrammed, EPROM'smay not have satisfactory data storage densities.

To avoid the complexity of EPROM's and to provide a device that can bereprogrammed in the field, many electronic designs use ElectricallyErasable Programmable Read Only Memory (“EEPROM”), Static Random AccessMemory (“SRAM”) or flash memory, which can be reprogrammed electricallyand without special hardware. SRAM is not technically a form ofnon-volatile memory but can be used in some applications requiringnon-volatile capability.

EEPROM has the disadvantages of being expensive and having a verylimited life cycle, i.e. an EEPROM can only be erased and rewritten alimited number of times before the device becomes non-functional. SRAMoffers high operating speeds but only maintains its contents as long aspower is supplied, therefore requiring a battery or other power source.This necessitates additional hardware to maintain power to the SRAM topreserve the stored contents which increases manufacturing cost andcomplexity. Further, the additional hardware may put undesirableconstraints on the physical size of the design. In addition, EEPROM'sand SRAM's may not have as high a data storage density when compared toother forms of storage. Therefore, where cost, size or density is afactor, flash memories are preferred because they may be simpler toreprogram in the field then EPROM's, less expensive than EEPROM's,easier to implement than battery-backed SRAM's and available in higherdata storage densities.

Flash memory (or flash RAM) is a form of non-volatile storage which usesa memory cell design with a floating gate. High voltages are applied tothe memory cell inputs to program/store charge on the floating gate orto erase/remove charge from the floating gate. Programming occurs by hotelectron transfer to place charge on the floating gate while erasuremakes use of Fowler-Nordheim tunneling in which electrons pierce througha thin dielectric material, reducing the amount of electronic charge onthe floating gate. Erasing a cell sets the logical value of the cell to“1” while programming the cell sets the logical value to “0”. Aside fromprogramming or erasing operations, a flash memory operates similarly toa randomly accessible read only memory (ROM). Conventionally, a flashmemory chip, including the flash memory storage cells and supportlogic/circuitry, is made by fabricating layers of semiconductor materialand interconnect layers of polysilicon and first and second metal layersonto a substrate. It will be appreciated that there are numerousintegrated circuit fabrication techniques, involving more or fewerlayers, which are applicable herein.

Prior flash memories could only be erased by erasing the entire memorychip also known as bulk erasure. Byte by byte erasure was not possible.To somewhat alleviate this problem, modern flash memory is typicallydivided logically into blocks called “sectors” where each sectorcontains a portion of the total bytes of data storage available. Forexample, a typical flash memory may have 32 megabits of total storageand be logically broken down into 64 sectors, each sector containing 64Kilobytes of data (one byte being equal to eight bits). This arrangementallows for the option of erasure of one sector at a time in addition tobulk erasure of the entire memory. While typical flash memories arestill incapable of byte by byte erasure, data in the flash memory maystill be programmed byte by byte (or sometimes word by word, where aword equals four bytes) depending on the implementation. It will beappreciated that the granularity by which a flash memory device can beprogrammed or erased may vary and that granularities down to bit levelprogramming/erasure are contemplated.

In order to program and/or erase a flash memory, typically a complexprocess must be followed. For example, before erasing a particularsector, that sector must be programmed (known as “pre-programming”).These steps of erasing and programming involve complex application ofhigh voltages to the memory cells for specified periods of time and inparticular sequences. Many flash memories provide embedded statemachines which perform the complex programming and erasing operationsautomatically. These processes of programming and erasing a flash memorymay take a long time to complete. A typical erase sequence can takeanywhere from 0.7 seconds up to 15 seconds per sector. To erase anentire chip can take up to 49 seconds depending on the number ofsectors. While programming is much faster, on the order of 7 to 300microseconds per byte, it is still slow compared to other memorydevices. Programming an entire chip can still take up to 120 seconds(including the time to verify the data) depending on the capacity of thechip. Typically, standard Dynamic Random Access Memory (“DRAM”) offerswrite access times on the order of nano-seconds, a difference whencompared to flash memory of many orders of magnitude.

This complex nature of programming and erasing flash memory devicesleads to a major problem in that they do not provide sufficiently fastwrite access which then affects read accesses. For example, conventionalflash memory devices typically do not allow a processor to perform aread operation while a program or erase operation is underway in theflash memory device. In most implementations, the processor is requiredto periodically poll a status register of the flash memory device todetect the end of the program or erase operation before initiating aread operation to the flash memory device.

Unfortunately, as noted above, the programming and erase cycle times fortypical flash memory devices are orders of magnitude greater thanacceptable write access times of a conventional random access mainmemory using, for example, Dynamic Random Access Memory (“DRAM”). Suchlong latencies associated with programming or erase operations can lockup the operating system and prevent the system from functioning forunacceptably long time intervals if the flash memory is the only memoryin the electronic system. Some prior flash memories allow erase suspendoperations in order to address this problem. Erase suspend allows theprocessor to pause an erase operation so another sector can be read.However, such memories typically still impose a suspend latency intervalof several microseconds before a read operation can be initiated. Atypical suspend latency interval is from 0.1 to 20 microseconds.

Prior systems may employ multiple flash memory devices in an attempt toprevent such operating system lock up. In such systems, the processorusually has read access to one of the flash memory devices while otherflash memory devices are undergoing a program or erase operation.However, such systems typically suffer from high costs because multipleflash memory devices are implemented even though the capacity of asingle flash memory device may accommodate the needs of the particularelectronic device.

Another prior art system uses a flash memory in combination with anEEPROM memory. This system allows a read operation of one of thememories while writing to the other. However, the size of an EEPROMmemory cell is significantly larger than that of a flash memory cellwhich reduces the amount of storage that can be placed on the memorychip. Further, there are significant design and manufacturingcomplexities involved with integrating two different memory technologieson the same chip. Therefore, a device which uses an EEPROM incombination with a flash memory will typically be more expensive both todesign and manufacture.

In addition, programming and erasing a flash memory involves higher thannormal voltages as compared to performing read operations. The use ofthese higher than normal voltages can cause problems when trying toimplement the capability to simultaneously read whileprogramming/erasing. Such problems include difficulties in distributingthe high voltages required for the program and erase operations alongwith normal voltage for read operations and handling increased noiseinduced on the read sense outputs by the use of high voltages elsewherewithin the device. Further, depending on the implementation, redundantlogic may also be employed which introduces further complexities.

Accordingly, there is a need for an efficiently designed andmanufacturable flash memory device that allows simultaneous read andwrite operations.

SUMMARY OF THE INVENTION

The present invention is defined by the following claims, and nothing inthis section should be taken as a limitation on those claims. By way ofintroduction, the preferred embodiments described below relate to asense pre-amplifier circuit to read a memory bank of variable size. Thesense pre-amplifier circuit comprises two inverting amplifiers, thesecond inverting amplifier providing a feedback loop for the firstinverting amplifier. In addition, special “kicker” circuitry raises thesense pre-amplifier's input signal line to its operating level. Thecombination of inverting amplifiers, feedback loop and level raisingcircuitry is configured to provide higher bandwidths for the sensepre-amplifier to accommodate low capacitive loading resulting from asmall memory bank. The combination is also configured to provide fasterraising of the input signal line to operating level to accommodate highcapacitive loading resulting from a large memory bank. The combinationis also configured to provide increased signal margins at the output ofthe sense pre-amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a block diagram of a flash memory chip according to thepresent invention that is capable of simultaneous reading and writing;

FIG. 2 depicts one of the upper read sense amplifiers.

FIG. 3 depicts one of the lower read sense amplifiers.

FIG. 4 depicts the circuitry of the upper sense pre-amplifier.

FIG. 5 depicts the circuitry of the lower sense pre-amplifier.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

Herein, the phrase “coupled with” is defined to mean directly connectedto or indirectly connected with through one or more intermediatecomponents. Referring now to the Figures and in particular, FIG. 1,there is schematically shown a flash memory device 100 according to thepresent invention that provides for reading while simultaneouslyundergoing a program or erase operation. The memory device 100 accordingto the present invention may include one or more components of thememory devices disclosed in U.S. Pat. No. 5,867,430 entitled “BANKARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING ANDWRITING,” to Chen et al and U.S. Pat. No. 5,847,998 entitled“NON-VOLATILE MEMORY ARRAY THAT ENABLES SIMULTANEOUS READ AND WRITEOPERATIONS,” to Van Buskirk, both of which are herein incorporated byreference and further describe the implementation and operation of adevice of this type. The memory device 100 may also include one or morecomponents of such exemplary flash memory devices capable ofsimultaneous read and write operation as the Am29DL162C and Am29DL163C16 megabit (“Mb”) flash memory chips and the Am29DL322C and Am29DL323C32 Mb flash memory chips manufactured by Advanced Micro Devices, Inc.located in Sunnyvale, Calif. For more detail regarding these exemplaryflash memory chips, refer to “Am29DL322C/Am29L323C 32 Megabit(4M×8-Bit/2M×16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation FlashMemory” Datasheet and “Am29DL162C/Am29L163C 16 Megabit(2M×8-Bit/1M×16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation FlashMemory” Datasheet. While the exemplary devices disclosed above havecapacities of 16 or 32 Mb, it will be appreciated that the embodimentsdisclosed herein are equally applicable to devices with higher bitdensities such as 64 or 128 Mb devices.

In a typical embedded application of the above exemplary simultaneousoperation capable flash memory 100, the available data storage space canbe structured to store data and boot code in one bank and control codein another bank. The control code, which can contain command sequenceswhich tell one bank, for example, bank 196, to program/erase datasectors, can reside as executable code in the alternate bank, forexample bank 194. While the first bank is being programmed/erased, thesystem can continue to execute code from the alternate bank to manageother system operations. Similarly, depending on the systemimplementation, the CPU can also execute code from the first bank whilethe alternate bank undergoes a program/erase. There is no bank switchinglatency and no need to suspend the program/erase operation to performthe read. This minimizes the CPU's read/write cycle time, maximizes datathroughput and reduces overall system cost by eliminating the need foradditional hardware. It will be appreciated that while the exemplarydevices have two banks of memory cells, devices with more than two banksare contemplated.

Again referring to FIG. 1, the memory device 100, according to anembodiment of the present invention with a capacity of 32 Mb andoperating in word addressable mode, includes a 21 bit address input 102,a 16 bit data input/output (“DATA”) 192, power inputs (not shown inFIG. 1) and control inputs (not shown in FIG. 1). It will be appreciatedthat the memory device 100 with a capacity of 16 Mb only requires 20address bits and when operating in byte mode, the 32 Mb device 100requires 22 address bits and the 16 Mb requires 21 address bits. Thecontrol inputs include Chip Enable, Output Enable, and Write Enable. TheChip Enable signal activates the chip's control logic and input/outputbuffers. When Chip Enable is not asserted, the memory device operates instandby mode. Output Enable is used to gate the outputs of the devicethrough I/O buffers during read cycles. Write Enable is used to enablethe write functions of the memory device. In one embodiment, all of thecomponents of FIG. 1 are contained on a single integrated circuit chip.Note that address and control inputs for the exemplary flash memorychips are dependent on memory density and interface implementations. Itwill be appreciated that the disclosed embodiments can work with highermemory densities and alternate interface implementations with theiraccompanying alternate address and control input configurations.

The memory device 100 further includes address buffer 104, addressmultiplexers 106 and 108, address sequencer 110, X logical addressdecoders 112 and 118, Y logical address decoders 114 and 120, memoryarray upper Bank 0 and lower Bank 1 denoted as 194 and 196 respectively,Dpump 160, data multiplexers 170 and 172, read sense amplifiers 174,verify sense amplifiers 176, negative pump 190, output multiplexer 180,state machine and control logic 122, input/output buffers 182, VPPIGPump 142, booster 0 denoted as 132, VPXGG Pump 134, booster 1 denoted as136 and power multiplexers 130, 138, 140 and 144. The address input 102is received by the address buffer 104, which sends the address to theaddress multiplexer 106 for bank 194 and the address multiplexer 108 forbank 196. The address sequencer 110 is controlled by the state machineand control logic 122. In one embodiment, the address sequencer 110 ispart of the state machine and control logic 122. The output of theaddress sequencer 110 is an address which is sent to both multiplexer106 and multiplexer 108. The address sequencer 110 is used to generatesequential addresses during an erase sequence. The output of themultiplexer 106, upper address UA, is communicated to the X addressdecoder 112 and the Y address decoder 114. The output of the multiplexer108, lower address LA, is sent to the X address decoder 118 and the Yaddress decoder 120. The multiplexer 106 chooses between the addressfrom the buffer 104 and the address from the address sequencer 110 inresponse to a control signal B0_SEL. The multiplexer 108 chooses betweenthe address from the address buffer 104 and the address from addresssequencer 110 based on a control signal B1_SEL. The selection signalsB0_SEL and B1_SEL are generated by the state machine and control logic122.

Bank 194 and bank 196 are arrays (or sets) of flash memory cells(operation of these individual flash memory cells is discussed in moredetail below). The banks 194, 196 are organized by words and then bysectors and can either be byte or word addressable. It will beappreciated by those skilled in the art that other types of non-volatilememory are also within the scope of the present invention. The addressdecode logic for bank 194 includes the X address decoder 112 and the Yaddress decoder 114. The X address decoder 112 includes a word linedecoder and sector decoder. The word line decoder receives address bitsUA[6:14] and the sector decoder receives address bits UA[15:20]. The Yaddress decoder 114 includes a bit line decoder and Y bit line gating.The bit line decoder receives address bits UA[0:5].

The address decode logic for bank 196 includes the X address decoder 118and the Y address decoder 120. The X address decoder 118 includes a wordline decoder and a sector decoder. The word decoder receives addressbits LA[6:14] and the sector decoder receives address bits LA[15:20].The Y address decoder 120 includes a bit line decoder and Y bit linegating. The bit line decoder receives address bits LA[0:5]. In oneembodiment, the address buffer 104 includes a latch to store the addressbeing decoded. In another embodiment, the latch can be part of thedecoders 112, 114, 118, 120.

FIG. 1 further shows a multiplexer 130 with three inputs: booster zero132, VPXGG pump 134 and Vcc. The VPXGG pump 134 is a positive powersupply for generating and supplying a regulated positive potential tothe control gate of selected flash memory cells via the word lines. Manydifferent voltage pumps known in the art are suitable for use in thepresent invention. A more detailed explanation of one technology whichcan be included in VPXGG pump 134 can be found in U.S. Pat. No.5,291,446, “VPP POWER SUPPLY HAVING A REGULATOR CIRCUIT FOR CONTROLLINGA REGULATED POSITIVE POTENTIAL” to Van Buskirk et al, the entirecontents of which are incorporated herein by reference. Booster 132 isused to boost the word line during reads. The multiplexer 130 receives aselection signal 197 from state machine and control logic 122 andchooses one of its three inputs to send to the word lines of bank 194via the X address decoder 112. The output of the multiplexer 130 islabeled as VPXG0. FIG. 1 is drawn to show the three inputs 132, 134 andVcc connected to a multiplexer in order to simplify the disclosure. Amore detailed description of one exemplary implementation can be foundin U.S. Pat. No. 5,708,387, “FAST 3-STATE BOOSTER CIRCUIT”, to Clevelandet al, the entire contents of which are incorporated herein byreference. Many booster circuits and selection circuits known in the artare suitable for use in the present invention.

FIG. 1 also includes another multiplexer 138 having three inputs:booster one denoted as 136, VPXGG pump 134 and Vcc. Booster 136 issimilar to booster 132. The multiplexer 138 operates in a similarfashion to multiplexer 130, and receives its selection signal 198 fromthe state machine and control logic 122. The output of multiplexer 138is VPXG1 which is sent to the word lines of bank 196 via the X addressdecoder 118. The purpose of the multiplexers 130 and 138 is to switchbetween the three power lines depending on the operation being performedon the particular bank of memory cells. The VPPIG pump 142 is a highvoltage pump used to pass high voltage to the drain of the memory cells.The output of the VPPIG pump 142 is sent to multiplexer 140 andmultiplexer 144. Both multiplexers also have Vcc as an input.Multiplexers 140 and 144 switch between inputs based on signals 195 and199 from the state machine and control logic 122. The output ofmultiplexer 140 is VPPI0 and the output of multiplexer 144 is VPPI1.During a normal read operation, VPPI1 and VPPI0 are connected to Vcc.VPPI0 is connected to the gate of an N-channel transistor 152. VPPI1 isconnected to the gate of an N-channel transistor 154. The source oftransistor 152 is connected to Y address decoder 114, multiplexer 170and multiplexer 172. The drain of transistor 152 is connected to theDpump 160 and the drain of transistor 154. The Dpump 160 is a drainpower supply. Various drain power supplies, known in the art, can beused for the present invention. One exemplary drain pump is disclosed inU.S. Pat. No. 5,263,000, “DRAIN POWER SUPPLY”, to Van Buskirk, et al.,the entire contents of which are incorporated herein by reference. Thesource of transistor 154 is connected to multiplexer 170 and multiplexer172. The source of transistor 154 is also connected to Y address decoder120 for purposes of accessing the bit lines in bank 196. The connectionsto multiplexers 170 and 172 provide a path for reading data from bank194 and bank 196. Multiplexer 170 uses the signal RSA_SEL from the statemachine and control logic 122 to selectively choose one of the two inputsignals to communicate to the read sense amplifiers 174. Multiplexer 172uses the selection signal VSA_SEL from the state machine and controllogic 122 in order to selectively communicate one of its two inputsignals to the verify sense amplifiers 176. Thus, the two transistors(152 and 154) and the two multiplexers (170 and 172), are used toselectively pass voltages to the drains of selected cells in bank 194 orbank 196 and to selectively read data from either bank 194 or bank 196.For the sake of clarity, the implementation of multiplexers 170 and 172is illustrative only. Some of the implementation details are not shownin FIG. 1. In the memory device 100, there are actually two sets ofsense amplifiers, one set for each bank 194, 196. There are also twosets of verify sense amplifiers. Data from the banks is multiplexed fromeach bank 194 or 196 to either its read sense amplifier or its verifysense amplifier. When a bank 194 or 196 is using its read senseamplifier, its verify sense amplifier is turned off and vice versa. Itwill be appreciated that there are many ways to multiplex multiple datasources among multiple destinations.

Data from either bank 194 or bank 196 can be communicated to either theread sense amplifiers 174 or the verify sense amplifiers 176. Both senseamplifiers are in communication with the state machine and control logic122. While data from bank 194 is communicated to the read senseamplifiers 174, data from bank 196 can be communicated to the verifysense amplifiers 176. While data from bank 194 is communicated to theverify sense amplifiers 176, data from bank 196 can be communicated tothe read sense amplifiers 174. The output of the verify sense amplifiers176 is sent to the state machine and control logic 122, which is used toverify that a particular byte has been programmed or erased. Note thatin the memory device 100, the preferred implementation of the read senseamplifiers 174 provides two sets of sense amplifiers, one for each bank194, 196. Only the sense amplifiers for the bank 194 or 196 undergoing aread operation are active during the read operation. The verify senseamplifiers 176 of the memory device 100 also have two sets of verifyamplifiers, one for each bank.

Data from the read sense amplifiers 174 is sent to multiplexer 180. Asecond input of the multiplexer 180 includes device 100 statusinformation from the state machine and control logic 122 such as whetheror not a program or erase is in progress. The selection signal formultiplexer 180 is provided by the state machine and control logic 122.

I/O buffers 182 are used to pass data out and receive data into memorydevice 100. While a read is being performed on one of the banks,multiplexer 180 will communicate output data from read sense amplifiers174 to I/O buffers 182. During an erase or program sequence, multiplexer180 will communicate status information to I/O buffers 182 so that anoutside processor can poll the memory device 100 for the status inregard to the erase or program.

The memory device 100 also includes a negative pump 190 that is used togenerate a relatively high negative voltage to the control gates ofselected memory cells via the word lines of either bank 194 or bank 196,as selected by the state machine and control logic 122. The negativepump 190 is in communication with the X address decoders 112 and 118.One example of a negative pump can be found in U.S. Pat. No. 5,612,921,“LOW SUPPLY VOLTAGE NEGATIVE CHARGE PUMP”, to Chang et al, the entirecontents of which are incorporated herein by reference.

The state machine and control logic 122 provides the control for read,program and erase operations. Many of the selection lines used to selectbetween bank 194 and bank 196 are controlled by the state machine andcontrol logic 122. Alternatively, the output from the X and Y addressdecoders 112, 114, 118, 120 can be used to select between banks ofmemory cells.

The memory device 100 is programmed using an embedded programmingsequence and is erased using an embedded erase sequence. The embeddedsequences allow a processor to initiate a program or erase sequence andperform other tasks while the program and erase sequences are beingcarried out. The embedded program and erase sequences are controlled bythe state machine and control logic 122, which uses a command registerto manage the commencement of either sequence. The erase and programmingoperations are only accessed via the command register which controls aninternal state machine that manages device operations. Commands arewritten to the command register via the data inputs 192 to the memorydevice 100.

While one bank is being programmed, the other bank can be accessed for aread operation. For example, during a program of a byte in bank 196, thestate machine and control logic 122 would cause multiplexer 108 toselect the address from buffer 104 for communication to decoders 118 and120. Further, the state machine and control logic 122 would store thedata byte to be programmed from the I/O buffers 182 for verificationwhen the programming completes. The output of bank 196 would be sent tothe verify sense amplifiers 176 via multiplexer 172 for comparison withthe stored input data. During a simultaneously initiated read operationto bank 194, the state machine and control logic 122, after storing awaythe data to be programmed, instructs multiplexer 106 to select theaddress from the buffer 104 for communication to the X and Y addressdecoders 112 and 114. The output of bank 194 would be sent to the readsense amplifiers 174 via multiplexer 170. The output of the read senseamplifiers 174 would be sent, via multiplexer 180, to the I/O buffers182 and then to the data bus 192.

Similarly, during an erase of a sector in bank 194, the state machineand control logic 122 would cause multiplexer 106 to select theaddresses from the address sequencer 110. The address sequencer 110would be used to cycle through all the bytes in a particular sector tomake sure that each byte is preprogrammed. The sector is subsequentlybulk erased. After erasure, the address sequencer 110 would be used togenerate addresses to verify each byte of this erased sector. While bank194 is being erased and multiplexer 106 is selecting an address from theaddress sequencer 110, a read operation can be carried out in bank 196by using multiplexer 108 to select the address from the buffer 104rather than an address from address sequencer 110. During the verifyoperation of the erase method for bank 194, the state machine andcontrol logic 122 would be verifying the data using the verify senseamplifiers 176, while read data from bank 196 would be communicated tothe read sense amplifiers 174. Thus, each bank has two input addresspaths and two output data paths that can be multiplexed so that eitherbank can be read from while the other bank is simultaneously beingwritten to.

In the memory device 100, each memory cell, within the banks 194 or 196,includes a nor-type floating gate transistor. It will be appreciated bythose skilled in the art, however, that there are many ways to implementa flash memory cell and that the configurations and operatingcharacteristics may vary. It will further be appreciated that theembodiments disclosed herein are generally applicable and not limited toone particular implementation of a flash memory cell. The exemplarytransistor has three connections called the source, drain and controlgate. In a typical flash memory array, the control gates of the memorycells are connected to the word lines of the array which are used toaddress the data stored in the array. The sources are selectivelyconnected to ground (for a read operation) depending on which bits areto be read. The drains are connected to the bit lines which are used tosense/read the stored data out of the array.

During an erase operation, the source input of the memory celltransistor is connected to a high positive voltage, the drain/bit lineis left to float and the control gate/word line is connected to arelatively high negative voltage supplied by the negative pump 190. Anexemplary high positive voltage applied to the source during an erase isapproximately 5 volts and an exemplary high negative voltage applied tothe control gate/word line by the negative pump 190 is approximatelyminus 9 volts although other voltages and input combinations can beused. Based on this input configuration, any charge stored on thefloating gate of the memory cell transistor will discharge by flowingout to the source due to Fowler-Nordheim Tunneling.

During a program operation, the source input of the memory celltransistor is connected to ground, the drain/bit line is connected to ahigh positive voltage provided by the VPPIG Dpump drain power supply 142and the control gate/word line is connected to a high voltage providedby the VPXGG pump positive power supply 134. An exemplary high voltageapplied to the drain by the VPPIG 142 is approximately 5 Volts while anexemplary high voltage applied to the control gate by the VPXGG 134 pumpis approximately 9 Volts. It will be appreciated by those skilled in theart that other voltage and input combinations can also be used. Based onthis input configuration, charge will flow by hot electron transfer tothe floating gate of the memory cell transistor and accumulate there.

While programming and erasing the memory cell require higher than normalvoltages, reading from the cell only requires the availability of thenormal supply voltage. To read from the memory cell, the source isconnected to ground (also referred to as Vss) and the control gate/wordline are connected to the booster power supplies 132, 136. Prior toselecting the transistors for a read, the bit lines are charged up viathe Dpump 160. When the cells turn on (if erased), they will connecttheir respective bit line to ground, grounding out the bit line. Thecurrent value of the memory cell is then sensed from the drain/bit lineconnection. There is a booster power supply 132 for bank 194 and abooster power supply 136 for bank 196. The booster power supplies 132,136 are used to boost the word lines of bank 194 or bank 196 during aread operation. An exemplary Vcc supply voltage is 3.0 Volts althoughother supply voltages are known in the art. An exemplary booster voltageis 5.0 Volts, although the use of the other voltages on the control gatefor read operations is possible. If there is charge stored on thefloating gate, i.e. the memory cell has been programmed, the flow ofcurrent from the drain to the source (ground) will be inhibited and thememory cell will read as a logical “0”. If the memory cell has beenerased, there will be no charge stored on the floating gate and with avoltage applied to the control gate greater than the threshold voltageof the transistor, current will flow from the drain to the source andthe memory cell will read as a logical “1”. Note that a transistor thatis on, grounds its respective bit line. Data read out of the array isconsidered in its complimentary form, therefore the grounded bit linesare interpreted as logical 1's and the non-grounded bit lines areconsidered logical 0's.

Application of the particular voltages necessary for each operation ishandled by the state machine and control logic 122. This logic 122controls the multiplexers 130, 138, 140, 144 that place the propervoltages from the various power supplies 132, 134, 136, 142 and Vcc onthe memory cell inputs depending on the desired function.

While the total capacity of the simultaneous read and write capableflash memory device 100 is 16 or 32 MB or higher, how that capacity isdistributed among the available banks is variable. Users of simultaneousread and write capable flash memory may need different bank partitionsizes depending on their applications. To meet the varying needs ofusers, the flash memory device 100 preferably implements a sliding bankarchitecture. This architecture allows the simplified design andmanufacture of simultaneous flash memory devices with varied bankpartition sizes. To alter the bank sizes, only a single metal layer ofthe chip needs to be altered. For a more detailed discussion of thesliding bank architecture, refer to co-pending and commonly assignedU.S. patent application Ser. No. 09/159,142, “SIMULTANEOUS OPERATIONFLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE”, filedSep. 23, 1998, U.S. patent application Ser. No. 09/159,029, “METHOD OFMAKING FLEXIBLY PARTITIONED METAL LINE SEGMENTS FOR A SIMULTANEOUSOPERATION FLASH MEMORY WITH A FLEXIBLE BANK PARTITION ARCHITECTURE”,filed Sep. 23, 1998 and U.S. patent application Ser. No. 09/159,489,“BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICEWITH A FLEXIBLE BANK PARTITION ARCHITECTURE”, filed Sep. 23, 1998, theentire contents of each of which are incorporated herein by reference.The sliding bank architecture enables the memory device 100 to beproduced in many different configurations with only a single mask changein one of the final steps of production. In the case where the flashmemory device 100 has a capacity of 32 megabits (Mb), partitions wherebank 194 has a capacity 4 or 8 Mb and bank 196 has a capacity of 28 or24 Mb respectively, can be used. In the case where the flash memorydevice 100 has a capacity of 16 Mb, partitions where bank 194 has acapacity of 2 or 4 Mb and bank 196 has a capacity of 14 or 12 Mbrespectively, can be used. This has the advantages that many differentconfigurations of the flash memory device 100 can share much of the samebasic design, process and manufacturing expense.

Turning to the present invention and FIG. 1, the flash memory device 100includes an array of memory cells or banks 194, 196 for storing bits ofdata. Two sets of read sense amplifiers 174, one upper 174U and onelower 174L, read the contents of these upper memory cells 194 and lowermemory cells 196. The memory device 100 employs a multitude of senseamplifiers 174, so that one read sense amplifier 174 is provided foreach of the memory device's data input/output pins 192. The flash memorydevice 100 may have both byte (eight bits) and word (sixteen bits)versions available where sixteen read sense amplifiers 174 (eight upperand eight lower) and thirty-two read sense amplifiers 174 (sixteen upperand 16 lower), respectively, are required.

FIGS. 2 and 3 show block diagrams of a member of the upper set of readsense amplifiers 174U and a member of the lower set of read senseamplifiers 174L, respectively. One of the upper read sense amplifiers174U is labeled USA_UNIT and one of the lower read sense amplifiers 174Lis labeled LSA_UNIT. Each of the upper and lower read sense amplifiersdepicted in FIG. 2 has two stages of amplification, a sensepre-amplifier and a sense output amplifier. Thus, USA_UNIT comprisesupper sense pre-amplifier 274U labeled Ucascodr and upper sense outputamplifier 295U labeled Usamp. Similarly, LSA_UNIT comprises lower sensepre-amplifier 274L labeled Lcascodr and lower sense output amplifier295L labeled Lsamp. The data output 296U from the upper sense outputamplifier 295U labeled UDSIBn and the data output 296L from the lowersense output amplifier 295L are communicated to multiplexer 180. Theinputs of the upper and lower sense output amplifiers derive, at leastin part, from the upper and lower sense pre-amplifiers, 274U and 274L,respectively, and are labeled USAin and LSAin, respectively. It will beappreciated that the sense output amplifiers may have additional inputsnot derived from the upper or lower sense pre-amplifiers.

FIGS. 2 and 3 also depict several input signals for the upper and lowersense pre-amplifiers. The data bit line signals 275U and 275L, labeledUDATABn and LDATABn respectively, communicate bit line information tothe upper and lower sense pre-amplifiers, respectively, from the upperand lower banks 194 and 196, respectively, via the multiplexers 170.

FIGS. 2 and 3 also depict input signals labeled URSTR 276U and LRSTR276L, which reset the upper and lower data bit lines to ground beforethe onset of the amplification function of the pre-sense amplifiers andwhich derive from portions of the circuitry not shown. Input signalslabeled UqBPDSA 277U and LqBPDSA 277L turn off the power to the uppersense pre-amplifier and lower sense pre-amplifier, respectively, whennot in use.

The internal circuit structure of the upper sense pre-amplifier labeledUcascodr is shown in FIG. 4 while the structure of the lower sensepre-amplifier labeled Lcascodr is shown in FIG. 5. The internal circuitstructure and operation of each circuit is identical; the operation willbe described in detail only for the upper sense pre-amplifier. All then-mos transistors are mid-voltage transistors with a gate oxidethickness that can tolerate up to about 12 volts applied between gateand source without damage or significant leakage; the n-mos transistorsare marked “mv” to describe this characteristic. The two p-mostransistors 318 and 319 are not so marked because their gate oxidethickness can support only a low voltage of up to about 3.5 volts.Transistors 311, 314 and 316 are marked with a “Z” to indicate that theyhave approximately a zero gate threshold voltage V_(t). Transistorsmarked with a “o” in the oxide but without a “Z” mark, 313 and 315, arecalled intrinsic transistors and have a gate threshold voltage V_(t) ofabout 0.4 volts. Transistor 310 has a threshold voltage of about 0.7-0.8volts.

In several embodiments voltage V_(cc) will range between about 2 volts(“low voltage”) and about 3 volts (“high voltage”), a considerablerange.

In each of these different voltage embodiments, the size of the bank 194and bank 196 can vary (as mentioned above). Preferably, in each of theseembodiments, the smaller of the two banks will be no smaller than 0.5Mb, while the larger will be no larger than about 32 Mb. Morepreferably, the smaller of the two banks will be no smaller than Mbwhile the larger of the two banks will be no larger than 28 Mb. Thus, inthe embodiments contemplated, the size of the banks varies in a widerange between 0.5 Mb and 32 Mb. This wide variation in bank size meansthat the capacitive loading on the bit lines communicating informationfrom the banks to the multiplexers 174 has a wide variation and,accordingly, the data bit lines carrying data bit line signals 275U and276L from the multiplexers to the upper and lower sense pre-amplifiershas a wide variation from low capacitance to high capacitance.

The wide variation in loading and voltages have been handled previouslyby adjustments in the metallization of the chip by changing the metalmasks. Changes in the metal masks are themselves inconvenient. Inaddition, chip fabrication requirements resulting from allowing a choiceof different metal masks produce additional use of chip space, whichreduces chip space available for important chip functions.

Transistors 311 and 314 form a first inverting amplifier, withtransistor 311 being the pull-up transistor and transistor 314 thepull-down transistor. Transistors 313 and 316 form a second invertingamplifier, with transistor 313 being the pull-up transistor andtransistor 316 the pull-down transistor. During a read operation, theinverting amplifiers are kept activated by a negative signal UqBPDSAwhich turns on transistors 318 and 319 connecting the invertingamplifiers to their power supply V_(cc).

The sense pre-amplifier 274U provides output USAin to upper sense outputamplifier 295U as mentioned earlier. However, the sense pre-amplifieralso brings up line UDATABn to its operating land from the groundvoltage created by signal URSTR before activation of the sensepre-amplifier. This level raising is accomplished quickly at almost thebeginning of the read cycle by the “kicker” circuit formed by high W/Ltransistor 313 and relatively high W/L transistor 315. As soon as node ais sufficiently high to turn on transistors 313 and 315, current quicklypasses from power supply V_(cc) through the low resistance paths formedby transistors 313 and 315, thereby quickly charging up upper databitline UDATABn to its operating level. This “kicker” function isespecially useful in situations when the capacitive loading on thebitline UDATABn is large because the size of the bank 194 being read islarge. This function is more useful yet when V_(cc) is low at about 2 Vbecause the other portions of the circuit do not operate as quickly atlow V_(cc), and the nodes of the circuit would only slowly bring theupper data bitline to its operating level.

The two inverting amplifiers forming the sense pre-amplifier areconfigured to form a feedback sense pre-amplifier. The first invertingamplifier of transistors 311 and 314 form a feedback network couplingthe output USAin via transistor 313 to the i/p UDATABn at node C.Feedback analysis of the sense pre-amplifier yields the result that theclosed loop small signal gain of the sense pre-amplifier isA_(c)(1+A_(i)), while the feedback loop gain is A_(c)A_(i). In thisexpression, A_(i) is the gain of the first inverting amplifier given byg_(m311)/g_(m314) while A_(c) is the gain of the second invertingamplifier given by g_(m3l3)/g_(m316). Accordingly, the small signal gainof the sense pre-amplifier is (g_(m313)/g_(m316)) [1+(g_(m311/g)_(m314))]. Similarly, the feedback loop gain is (g_(m313)/g_(m316))(g_(m311)/g_(m314)). Transistor 314 is sized in its W/L ratio to providehigh g_(m314) an objective furthered by its approximately zero V_(t).Transistor 316 is sized with a relatively low W/L ratio to provide arelatively smaller g_(m316). Transistor 311 is sized with a relativelylow W/L ratio to provide relatively low g_(m311), an objective furtheredby its approximately zero V_(t). Accordingly, A_(i) is relatively lowand A_(c) is relatively high resulting on balance in a relatively lowfeedback loop gain A_(c)A_(i) and also a relatively low closed loopsmall signal gain A_(c) (1+A_(i)). As a result of the constant gainbandwidth product law, the bandwidth of the feedback loop and also theentire sense pre-amplifier circuit is increased resulting in fastercircuit response to handle the situation when the capacitive loading onthe data bitline UDATABn is low because the size of the bank 194 beingread is small. Without that faster circuit response, the data bitlineoperating level would be reached before all the other nodes of the sensepre-amplifier circuit had reached their operating levels. Were thatcircuit lag to occur, the likelihood of glitches at the nodes or USAinoutput amplifier would increase. On the other hand, because the gain Acis higher, better USAin noise margins result.

The relatively low feedback loop gain means a lower voltage at node a.This low voltage at node a taken together with the approximately zeroV_(t) is sufficient to bias pull-up transistor 311 even though Vgs fortransistor 311 is relatively small, especially if V_(c) is about 2V.

It is to be noted that suitable transistor sizes specifying channelwidth to length ratios (measured in micrometers or microns) for thetransistors which make up the depicted circuits have been omitted fromthe figures. It will be appreciated that suitable ratios may be chosendepending on the design requirements and the capabilities andlimitations of the particular integrated circuit fabrication processused for implementation of the circuit as well as the performancerequirements of the specific embodiment.

It is therefore intended that the foregoing detailed description beregarded as illustrative rather than limiting, and that it be understoodthat it is the following claims, including all equivalents, that areintended to define the spirit and scope of this invention.

What is claimed is:
 1. A sense pre-amplifier circuit for a flash memorydevice capable of simultaneous operation, the flash memory device havinga first memory bank of flash memory cells and a second memory bank offlash memory cells, the sense pre-amplifier circuit comprising: a firsttransistor having a gate, drain and source, wherein the gate of saidfirst transistor is coupled to the first memory bank at the input of thesense pre-amplifier, and the source of said first transistor is coupledto ground; a second transistor having a gate, drain and source, whereinthe source of said second transistor is coupled to the drain of saidfirst transistor and the drain of said second transistor is selectivelycoupled to a voltage source with a voltage level V_(cc), the first andsecond transistors together forming a first inverting amplifierproviding a feedback; a third transistor having a gate, drain, andsource, wherein the gate of said third transistor is coupled to thedrain of said first transistor, and the source of said third transistoris selectively coupled to ground and also coupled to the gate of saidfirst transistor, wherein the gate of said third transistor is coupledto the source of said third transistor by said feedback network; afourth transistor having a gate, drain, and source, wherein the drain ofsaid fourth transistor is selectively coupled to the voltage source, andthe source of said fourth transistor is coupled to the drain of saidthird transistor, thereby forming a second inverting amplifier, and alsocoupled to the output of said sense pre-amplifier; and a fifthtransistor having a gate, drain, and source, wherein the gate of saidfifth transistor is coupled to the drain of said first transistor, andthe drain of said fifth transistor is selectively coupled to the voltagesource, and the source of said fifth transistor is coupled to the drainof said third transistor.
 2. The sense pre-amplifier circuit accordingto claim 1, wherein the first, second, third, fourth, and fifthtransistors are intrinsic transistors.
 3. The sense pre-amplifiercircuit according to claim 2, wherein the first, second and fourthtransistors are Z-type transistors.
 4. The sense pre-amplifier circuitaccording to claim 3, wherein the first, second, third, fourth, andfifth transistors are midvoltage transistors.
 5. The sense pre-amplifiercircuit according to claim 4, wherein the voltage source is in the rangeof about 2 volts to 3 volts.
 6. The sense pre-amplifier circuitaccording to claim 4, wherein the voltage source is about 3 volts. 7.The sense pre-amplifier circuit according to claim 4, wherein thevoltage source is about 2 volts.
 8. The sense pre-amplifier circuitaccording to claim 5 wherein the first transistor and second transistorhave sufficiently low and high g_(m), respectively, to provide thefeedback network with a low feedback loop gain and to provide the closedloop sense pre-amplifier circuit with a low circuit gain, the lowfeedback loop gain and low closed loop sense pre-amplifier circuit gainbeing sufficiently low to increase the bandwidth of the sensepre-amplifier circuit.
 9. The sense pre-amplifier circuit according toclaim 1 wherein the fourth transistor has a sufficiently low g_(m) toincrease the noise margins of the second inverting amplifier and thesense pre-amplifier circuit.
 10. A sense pre-amplifier transistorcircuit coupled to a voltage source with a voltage level V_(cc), for aflash memory device capable of simultaneous operations, the flash memorydevice having a first memory bank of flash memory cells and a secondmemory bank of flash memory cells, the sense pre-amplifier circuitcomprising: a feedback network comprising a first inverting amplifierhaving an input, wherein said feedback network is coupled to the inputand output of a second inverting amplifier having an input and output,and wherein the input of said first inverting amplifier is coupled tothe input of said second inverting amplifier.
 11. The sensepre-amplifier transistor circuit according to claim 10, furthercomprising a low feedback loop gain and a low closed loop small signalgain.
 12. The sense pre-amplifier transistor circuit according to claim11 wherein the second inverting amplifier has a sufficiently high gainto increase the noise margins of the second inverting amplifier and thesense pre-amplifier.
 13. The sense pre-amplifier transistor circuitaccording to claim 10, wherein all the transistors are intrinsictransistors.
 14. The sense pre-amplifier transistor circuit according toclaim 10, wherein at least one of the transistors is a Z-typetransistor.
 15. The sense pre-amplifier transistor circuit according toclaim 10, wherein at least one transistor is a midvoltage transistor.16. The sense pre-amplifier transistor circuit according to claim 10,wherein V_(cc) is in the range of about 2 volts to 3 volts.
 17. Thesense pre-amplifier transistor circuit according to claim 16, whereinV_(cc) is about 3 volts.
 18. The sense pre-amplifier transistor circuitaccording to claim 16 wherein V_(cc) is about 2 volts.